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High-Density Packaging Accelerates in Semiconductor Devices

Fig. 2: Cross section of a motherboard for smartphones
Fig. 2: Cross section of a motherboard for smartphones

Technologies that drew attention at JPCA Show 2018 held in Tokyo in June will be described below.

During a symposium, Intel Corporation announced its strategy on heterogeneous integration technology for semiconductor chips on the latest package substrates [three-dimensional silicon in a package (3D-SiP)] toward the 5G era. The package called embedded multi-die interconnected bridge (EMIB) uses proven integration technology to create 3D analog and digital semiconductor chips, which were previously non-existent, in order to improve performance and bandwidth.

Through high integration, EMIB shortens wiring distance and hence reduces power consumption, saves board space, secures scalability, and reduces costs of components constituting the entire boards.

Mitsui Mining & Smelting Co., Ltd. introduced a technology for line/space (L/S) of 30μm/30μm, which is a yardstick of fine fabrication, in promoting finer fabrication of motherboards for smartphones and other electronic devices that are packaged with increasing density. The technology adopts the modified semi-additive process (MSAP), which is a plating method based on the company's MicroThin ultra-thin copper foil to form wirings.

The company also exhibited a high-resolution de-bondable panel (HRDP), a material for forming fine circuits with glass carrier for fanout panel-level-packaging (FO-PLP) that supports high-density wiring and multipins for substrates for packages.

A company spokesperson said HRDP improves the yield and manufacturing costs of the Chip 1st method, in which semiconductor chips are first arranged on the carrier in the packaging process. The redistribution layer 1st (RDL 1st) method, wherein a redistribution layer is formed first, has reduced the loss of good-quality chips as semiconductor chips are mounted after the formation of the RDL, and improved the yield, making cost reduction possible. It has been confirmed that using HRDP enables the formation of fine wiring with a L/S ratio of around 2/2μm.

Okuno Chemical Industries Co., Ltd. introduced the desmear non-electrolytic plating method, which is optimal for the MSAP method. This process combines non-electrolytic copper plating using nanosilver catalyst and the company's original flash etching. The company showed the possibility of achieving L/S of 1μm/1μm. The conventional non-electrolytic plating used palladium (Pd) catalyst. However, as the removal of Pd in the subsequent etching process is difficult, it was considered that circuits with L/S of 5μm/5μm or finer were challenging.

This time, Okuno Chemical said that it has achieved L/S of 1μm/1μm using silver nanoparticle catalyst, and performing copper sulfate plating, and flash etching, which resulted in less catalyst residue and less precipitation outside the pattern.

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